1. Field of the Present Invention
The present invention relates to semiconductor integrated circuit (IC) devices, and, more particularly, to a simplified design and process for providing appropriate electrical isolation between adjacent transistors and reduced parasitic capacitances in such devices.
2. Description of the Prior Art
A continuing trend in the design of ICs, particularly CMOS ICs, is toward lower operating voltages, shorter channel lengths, and thinner gate dielectrics. For example, the presently standard 5 volt power supply for CMOS logic and memory circuits is being replaced by a 3.3 volt supply, and there are predictions that future ICs, with even shorter channel lengths, much less than 1.0 micron, will operate at 2 volts or less.
For CMOS ICs having effective channel lengths of about 1.0 micron or less, it is conventional to use a twin well approach, with both wells having a surface doping concentration in the range of 1.times.10.sup.17 atoms/cm.sup.3 to 4.times.10.sup.17 atoms/cm.sup.3, the lesser concentration being useful for effective channel lengths down to about 0.6 micron, and the greater concentration being useful for effective channel lengths, between about 0.6 micron and 0.3 micron. The nMOS transistors are fabricated in the P-doped well (p-well), and the pMOS transistors are fabricated in the N-doped well (n-well). Each p-well functions as a common body connection for all of the nMOS transistors in that p-well, and often is connected to the most negative supply voltage. Each n-well functions as a common body connection for all of the p-MOS transistors in that n-well, and often is connected to the most positive of the supply voltages.
Typically, the field oxide between adjacent transistors is at least 5000 Angstroms thick to avoid field inversion and provide good electrical isolation. In addition to this relatively thick oxide, it is common practice to selectively implant with boron those portions of the p-well silicon surface under the field oxide to even larger doping levels than the original p-well doping levels. These larger doping levels aid in achieving a sufficiently large field inversion voltage between adjacent nMOS transistors, to ensure adequate electrical isolation. This extra implant usually is necessary only for the p-well because a P-type surface tends toward inversion, whereas an N-type surface tends toward enhancement. As is well known, this tendency for a p-well surface to invert is primarily due to some amount of unavoidable Si-SiO.sub.2 positive interface charge (Q.sub.SS).
A principal disadvantage to the use of the extra boron implant, in addition to its cost and complexity, is that the source and drain junction sidewall capacitance, commonly termed one of the "parasitic capacitances," of the nMOS transistors is significantly increased, often to twice the amount such capacitance would otherwise be, as a result of the increased amount of doping. This extra capacitance causes substantial speed degradation in some products, such as memory chips with long bit lines. Another disadvantage is that the extra boron doping in the field region can diffuse sideways and reduce the effective channel width (W) of the active transistors.
In addition to the extra boron implant, many IC products use a negative back bias (V.sub.B) applied to the p-well to increase the field inversion voltage between the nMOS transistors. Less boron field doping needs to be implanted if this is done. Another advantage of using the negative back bias is that the sidewall capacitances and other parasitic capacitances, such as the bottom capacitances, associated with the sources and drains, are reduced approximately in inverse proportion to the square root of the amount of applied back bias.
Typically, the negative back bias voltage is generated by a charge pump circuit integrated onto the same chip as the rest of the circuitry. As is well known, the charge pump circuitry typically operates between the power supply voltage and a ground reference voltage connected to the overall IC chip, and typically includes an oscillator and other circuitry to maintain a negative voltage on a capacitor (which alone occupies considerable silicon area). The thus-generated negative voltage is applied to the p-well. Inasmuch as the p-well typically is conductively die-attached to the IC package, the floor of the overall package (or IC housing) is thereby pumped approximately to that same negative voltage.
A principal disadvantage of using charge pumps is that they typically cannot supply very much current, which can be a serious problem for some of the newer processes with short channel lengths and large hot carrier-induced substrate current. Another disadvantage of the known on-chip charge pumps is that they consume chip area. This problem is more serious in ICs that use multiple charge pumps.
It has been conventional in CMOS processing to use the "LOCOS" process, in which the field oxide is grown while the active regions are masked against oxidation by a selectively formed coating of silicon nitride. The LOCOS process, without extra complicated refinements, has the disadvantage of field oxide encroachment into the active areas, which reduces the effective channel width (W) dimension of the active transistors. An additional disadvantage of the conventional LOCOS-based processes is that excess strain typically is induced in the silicon near the edges of the portions where the oxide growth is masked by the nitride. This strain is known to produce many dislocations in the crystalline material, which can reduce yield.